Strained-Si CMOS Technology -- High Current Drivability MOSFET Fabricated on Si(110) Surface -- Advanced High-Mobility Semiconductor-on-Insulator Materials -- Passivation and Characterization of Germanium Surfaces -- Interface Engineering for High-? Ge MOSFETs -- Effect of Surface Nitridation on the Electrical Characteristics of Germanium High-?/Metal Gate Metal-Oxide-Semiconductor Devices -- Modeling of Growth of High-? Oxides on Semiconductors -- Physical, Chemical, and Electrical Characterization of High-? Dielectrics on Ge and GaAs -- Point Defects in Stacks of High-? Metal Oxides on Ge: Contrast with the Si Case -- High ? Gate Dielectrics for Compound Semiconductors -- Interface Properties of High-? Dielectrics on Germanium -- A Theoretical View on the Dielectric Properties of Crystalline and Amorphous High-? Materials and Films -- Germanium Nanodevices and Technology -- Opportunities and Challenges of Germanium Channel MOSFETs -- Germanium Deep-Submicron p-FET and n-FET Devices, Fabricated on Germanium-On-Insulator Substrates -- Processing and Characterization of III–V Compound Semiconductor MOSFETs Using Atomic Layer Deposited Gate Dielectrics -- Fabrication of MBE High-? MOSFETs in a Standard CMOS Flow.

Will nanoelectronic devices continue to scale according to Moore’s law? At this moment, there is no easy answer since gate scaling is rapidly emerging as a serious roadblock for the evolution of CMOS technology. Channel engineering based on high-mobility semiconductor materials (e.g. strained Si, alternative orientation substrates, Ge or III-V compounds) could help overcome the obstacles since they offer performance enhancement. There are several concerns though. Do we know how to make complex engineered substrates (e.g. Germanium-on-Insulator)? Which are the best interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? Can we process these materials in short channel transistors using flows, toolsets and know how similar to that in Si technology? How do these materials and devices behave at the nanoscale? The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any close to a viable Ge and III-V MOS technology.