Verification by error modeling [electronic resource] : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.

By:

Contributor(s):

Series: Frontiers in electronic testing ; 25.Publication details: Boston : Kluwer Academic Publishers, 2003.Description: xiv, 216 p. : illISBN:

Subject(s):

Genre/Form:

DDC classification:

LOC classification:

Online resources:

Item type:

eBooks

Average rating: 0.0 (0 votes)

No physical items for this record

Includes bibliographical references and index.

Electronic reproduction. Palo Alto, Calif. : ebrary, 2013. Available via World Wide Web. Access may be limited to ebrary affiliated libraries.

Back to results