VLSI Systems -- Signal Delay in VLSI Systems -- Timing Properties of Synchronous Systems -- Clock Skew Scheduling and Clock Tree Synthesis -- Clock Skew Scheduling of Level-Sensitive Circuits -- Clock Skew Scheduling for Improved Reliability -- Delay Insertion and Clock Skew Scheduling -- Practical Considerations -- Clock Skew Scheduling in Rotary Clocking Technology -- Experimental Results.

Timing Optimization Through Clock Skew Scheduling focuses on optimizing the timing of large scale, high performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits. This research monograph answers the need for a broad introduction to state-of-the-art clock skew scheduling algorithms from a circuit, graph, and mathematical optimization background. A detailed description of clock skew scheduling application on edge-triggered and level-sensitive circuits, synchronized with single and multi-phase clocking schemes, and formulated as linear programming (LP) and quadratic programming (QP) formulations are provided along with an analysis of optimal computer solution techniques. Theoretical limits of improvement in clock frequency through clock skew scheduling are highlighted. Hints and a preliminary implementation of a parallel skew scheduling application are also included. Timing Optimization Through Clock Skew Scheduling contains sufficient detail for the advanced CAD algorithm developer, researcher and graduate student. Furthermore, with the material provided on timing properties and optimization, those readers with less background can also benefit from this book.